The present invention relates to a digital filter processing device for digitally filtering data signal by the combination of multipliers, adders, and the like.
FIG. 2 shows in block form a conventional digital filter processing device. The device is a one-dimensional digital filter processing device with five taps. This type of the device is frequently fabricated into an LSI (large scale integrated circuit).
In FIG. 2, reference numerals 1--1 to 1-4 designate delay circuits; 2-1 to 2-5, coefficient registers 3-1 to 3-5, multipliers; 4, an adder; 5, a CPU (central processing unit) interface; 6, an input terminal; and 7, an output terminal.
A data signal applied to the input terminal 6 propagates through the delay circuits 1--1 to 1-4 while being successively delayed in synchronism with a clock signal (not shown). With the propagation, the data signal is also successively applied to multipliers as are provided in connection with the delay circuits. For example, the output data signal of the delay circuit 1--1 is transferred to the delay circuit 1-2, and also to the multiplier 3-2 provided in connection with the delay circuit.
With the connection of the delay circuits and the multipliers, the data signal outputted from the delay circuit 1-4 is the data as inputted four clocks ago. At that time, a total of five data signals as have been inputted for the past four clocks are inputted to the multipliers 3-1 to 3-5 simultaneously.
The coefficient data to be subjected to the muItiplications for digital filter processing are stored in the coefficient registers 2-1 to 2-5. The coefficient data may be loaded into the registers through the CPU interface, from the CPU. The coefficient data stored are respectively transferred to the corresponding multipliers where those items of data are multiplied by the data signals.
The results of the multiplications are added together by the adder 4. The output data of the adder is outputted as filter output data from the output terminal 7.
The delay circuits 1-1 to 1-4 are provided for applying the results of the multiplications of the five data signals to the adder at the same timings. If the multiplication results reach the adder at the different timings, the adder improperly functions.
An example of the articles discussing the digital filter processing device is a paper entitled "A High Speed CMOS Digital Filter LSI for Video Signal Processing" by Hideki Kokubun et al., in THE INSTITUTE OF ELECTRONIC AND COMMUNICATION ENGINEERS OF JAPAN RESEARCH REPORT, SSD86-44.
The above prior art involves the following problems.
First, a quantitizing error (to be described in detail later) of the coefficient data set in each coefficient register is large. This error is amplified and accumulated during the course of the filter arithmetic operation, and finally the filter output data contains a large error.
Second, the decimal point of the filter output data is fixed at a value which depends on the coefficient data. Accordingly, the dynamic range (a range of expressible numerical values) of the filter output data is limited by the fixed decimal point.
(1) The first problem will be described.
To express the coefficient data necessary for an ideal filter processing in terms of a chain of bits, a length of the bit chain is infinite.
The coefficient registers 2-1 and the like for storing the coefficient data are equal in length of the bits. Consequently, of the coefficient data, only the data in the fixed bit length as counted from the most significant bit are stored in the registers. Such a process means the quantitizing of the coefficient data.
As the result of the quantitizing, a value of the data as expressed by a stream of bits, which includes the bit at the position where the fixed bit length terminates, and the bits at the positions of lower order than the position of the former bit is neglected. The neglected value is the error arising from the storage of the coefficient data (i.e., the error due to the quantitization of the coefficient data).
The first problem will be further described by using a specific example.
FIGS. 3(a) through 3(c) show explanatory diagrams useful in explaining how the coefficient data is stored in the coefficient register.
FIG. 3(a) indicates values of the coefficient data to be stored in the coefficient registers. The coefficient data A.sub.1 is to be stored in the coefficient register 2-1. The coefficient data A.sub.2 is to be stored in the coefficient register 2-2. In this instance, only 8 bits up to the 8th decimal place are written for the coefficient data A.sub.1. Only 11 bits up to the 11th decimal place, for the coefficient data A.sub.2. However, it can be considered that the bit stream of each data is followed by a stream of O's whose length is infinite.
In case that each coefficient register for storing the coefficient data, for example, the register 2.1 is an 8-bit one, the data to be stored is a part of the data as enclosed by a solid line as shown in FIG. 3(b). As seen, if the bit stream of the data from the first decimal place is stored, all of the bits shown in FIG. 3(a) are stored as for the coefficient data A.sub.1, while the bits from the 9th to 11th decimal places are discarded as for the coefficient data A.sub.2. The discarded bits constitute an error.
This error is amplified through the multiplication by the multiplier 3-1, and is added together with the errors outputted from the other multipliers, in the adder 4. As a consequence, the filter output data derived from the output terminal 7 inevitably contains an error.
(2) The second problem will be described in detail.
If the input data is an integer value, the position of the decimal point of the multiplication result outputted from the multiplier 3-1 is determined depending or the position of the decimal point of the coefficient data stored in the coefficient register 2-1. The same thing is true for the multiplication results of the remaining multipliers.
When the decimal point of the coefficient data is located at the position on the left side of the Nth bit as counted from the least significant bit, the decimal point of the multiplication result is located at the same position.
In the adder 4, the data in which the positions of the decimal points are thus determined are added together. Accordingly, the position of the decimal point of the filter output data resulting from the addition is automatically and fixedly determined by the position of the decimal point of the coefficient data.
This fact implies that a magnitude of the filter output data, viz., the dynamic range of it, is automatically determined by the position of the decimal point of the coefficient data.
The second problem will be further described using a specific example.
FIGS. 5(a) and 5(b) show explanatory diagrams for explaining how the dynamic range depends on the position of the decimal point. In the figure, each square indicates one bit. In the instance of FIG. 5, the filter output data consists of 10 bits. In the data of FIG. 5(a), the decimal point is located on the left side of the 4th bit position as counted from the least significant bit. The decimal point of the data of FIG. 5(b) is located on the left side of the 6th bit position as counted from the least significant bit. When comparing the two different data with each other, the data of FIG. 5(a) contains six bits to the left from the decimal point, while the data of FIG. 5(b) contains only four bits. A value that can be expressed by the data format of FIG. 5(a) is smaller than that by the data format of FIG. 5(b). The dynamic range of the data in FIG. 5 (a) is smaller than that in FIG. 5(b).
A desired dynamic range depends on a frequency band of the digital filter and a value of the coefficient data to be used. In the conventional digital filter processing device, the dynamic range is fixedly determined by the position of the decimal point of the coefficient data. Accordingly, it frequently fails to obtain a desired dynamic range.